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RAM
SPD is programmed to JEDEC standard latency DDR4-2666 timing of19-19-19 at 1.2V. Each 288-pin DIMM uses gold contact fingers. Theelectrical and mechanical specification s are as follows:FEATURES• Power Supply: VDD=1.2V Typical• VDDQ = 1.2V Typical• VPP - 2.5V Typical• VDDSPD=2.2V to 3.6V• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals• Low-power auto self refresh (LPASR)• Data bus inversion (DBI) for data bus• On-die VREFDQ generation and calibration• Single-rank• On-board I2 serial presence-detect (SPD) EEPROM• 16 internal banks; 4 groups of 4 banks each• Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS)• Selectable BC4 or BL8 on-the-fly (OTF)• Fly-by topology• Terminated control command and address bus• PCB: Height 1.23” (31.25mm)• RoHS Compliant and Halogen-Free
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